used in capturing data at the receiver8) Data inputs and outputs are synchronzed with DQS.9) DQS is edge aligned with data for read, center aligned with data for write.10) Differential clock inputs (CK and CK)11) DLL aligns DQ and DQS transitions with CK transitions12) Commands entered on each positive CK edge: Data and data mask referenced to
both edges of DQS.13) Four internal banks for concurrent operation (component) 14) Data mask(DM) for write data. 15) Auto precharge option for each burst access16) Programmable burst length: 2, 4, 8 17) Programmable/CAS latency (CL): 3 18) Programmable output driver strength: Normal/weak 19) Refresh cycles: (8192 refresh cycles/64ms) .20) 7.8US maximum average periodic refresh interval.21) Posted CAS by programmable additive latency for better command and data bus
efficiency 22) Off-chip-driver impedance adjustment and on-die-termination for better signal quality .23) DQS can be disabled for single-ended data strobe operation 24) 2 variations of refresh25) Auto refresh 26) Self refresh